DC power converter circuit

ABSTRACT

A self oscillating power converter uses two MOSFET transistors connected across first and second primary windings. Each MOSFET is controlled using a gate control circuit located in a feedback path. Each gate control circuit is driven by a gate drive winding which is transformer coupled to a primary winding and which is phased with the primary winding such that regenerative feedback causes accelerated sequential turn-on and turn-off of the associated MOSFET transistor. Each feedback path includes a capacitor for charging in response to the voltage generated across the gate drive winding to initiate turn-on of the MOSFET transistor and a resistor for discharging the capacitor to initiate turn-off of the MOSFET transistor. The power converter can be configured as a push-pull converter in either a common-drain or common-source configuration. The power converter can also be configured such that at least one MOSFET transistor is capacitively coupled to a primary winding. Further, the power converter can be configured as either a full-bridge or a half-bridge converter.

CROSS-REFERENCE TO PREVIOUS PROVISIONAL APPLICATION

This application claims the benefit of priority from U.S. ProvisionalApplication No. 60/114,864, filed Jan. 6, 1999.

FIELD OF THE INVENTION

The present invention relates generally to self oscillating powerconverters and more particularly to an improved self oscillating circuitfor power converters.

BACKGROUND OF THE INVENTION

As the number of electronic devices continue to multiply in residentialand office environments, the adverse effects of electro-magneticinterference (EMI) noise from one piece of equipment on other nearbyequipment are becoming more problematic. As a result, restrictions onpermissable EMI levels produced by electronic devices are becoming morestringent which in turn is producing significant demand forhigh-efficiency power converters with appropriately reduced EMIemissions.

Forced oscillation converters are commonly used in high efficiency powersupplies. This type of converter generally comprises an input rectifierand filter, high frequency inverter, control circuit and an outputsection. Typically, high frequency MOSFET switches are operated byvarying duty cycle or frequency to maintain the output voltage at adesired level. The efficiency of such converters is limited by losses inthe MOSFETs during turn-on and turn-off, particularly in pulse-widthmodulated (PWM) converters. Since the primary current of a powertransformer is periodically interrupted by high voltage spikes, EMI isproduced. In the case of balanced converters, it is difficult to achievesynchronized opening and closing of the MOSFET switches due to straycapacitances, inductance and noise, complex control circuity forproviding properly formed and timed DC pulses is generally required.These conditions require the addition of numerous interferencesuppressor and protection circuits and result in increased convertersize and complexity. Methods for reducing EMI for forced oscillationpower converters include the use of snubbers, input filters as well asadoption of special control strategies. However, these methods furthercomplicate the design process and appreciably increase production cost.

Self oscillating converters do not utilize as many components as forcedoscillation converters and may not generate such high levels of EMI,however they suffer from switching speed limitations and powerinefficiencies. Transformer coupled self oscillating converters aredesigned to trigger switching transistor turn-on and turn-off usingeither the saturation of the switching devices, saturation of the powertransformer core, or saturation of an intermediate drive transformer.The technique of saturation switching transistors is limited to slowerswitching speeds and the energy required to fully saturate transformerscauses power losses and results in compromised efficiencies.

Specifically, a longstanding type of self oscillating DC to DC converteris disclosed in U.S. Pat. No. 5,303,137 to Peterson. Peterson utilizes aMOSFET half-bridge configuration in which each transistor is alternatelysaturated. Once a transistor is saturated, current continues to flow inthe transformer winding due to the magnetizing inductance of transformerand the reflected load current. This current discharges the voltageacross a circuit capacitor to reduce the voltage across the primarywinding, which in turn is coupled to the gate windings. As the currentrises, the transistor comes out of saturation and turns itself on againcausing a voltage drop to reappear across the transformer. However,since this switching technique relies on the transistor beta factor itcannot be implemented using MOSFETs and higher switching frequenciescannot be achieved.

Another type of self oscillating circuit drives transistor switchesusing the properties of core saturation, as described in U.S. Pat. No.4,319,315 to Keeney, Jr. et al., where a DC to DC converter uses asaturable transformer having a center-tap and resistive networkinterposed among four sequentially operating transistors. Thetransistors cause one side of the input DC voltage to be sequentiallyapplied to opposite sides of a primary winding of the transformer which,in turn, cause the transformer to be excited into positive and thennegative saturation conditions. When the transformer core saturates,appropriate gate drive voltages collapse and the associated transistorsswitches are turned off. While core saturating transformer convertersare simpler than forced oscillating converters, since the core must befluxed from one end to another in order to fully saturate, significantpower losses result and overall efficiency is reduced.

Finally, another type of self oscillating converter utilizes resonanceeffects within an oscillating circuit, such as the converter disclosedin U.S. Pat. No. 5,430,632 to Meszenyi where a pair of MOSFETtransistors are configured in a half-bridge configuration and coupled toa reactive network. The frequency of oscillation is determined by thegate-to-source capacitance of the transistors and the inductance of thedrive transformer. This resonance converter suffers from increasedcomplexity, sensitivity to parasitics and emissions due to its highoperating frequency.

Thus, there is a need for a self oscillating power converter whichachieves conventional power efficiencies using a minimal number ofparts, which generates a significantly reduced amount of EMI, whichprovides increased reliability, and which can be operated at slowerswitching speeds to further reduce EMI emissions.

BRIEF SUMMARY OF THE INVENTION

Accordingly, it is an object of the present invention to provide arelatively simple self-oscillating DC power converter circuit whichoscillates at lower switching speeds to provide reduced EMI and has anon-saturating transformer to reduce power losses.

One embodiment of a circuit according to the present invention providesa DC output voltage which corresponds to a DC input voltage. The inputDC voltage is alternately switched across a pair of primary windings ofa transformer. A secondary output winding is coupled to each of theprimary windings. A secondary voltage appears across each of thesecondary output windings as the input DC voltage is switched across thecorresponding primary winding. The secondary voltages are rectified andprovide the DC output voltage. The DC output voltage corresponds to theinput DC voltage, based on the turns ratio of the primary windings tothe secondary output windings. The switching of the input DC voltageacross the primary windings is controlled by alternately switching twoMOSFET transistors. Each transistor is coupled to one primary winding sothat a greater amount of the DC input voltage is seen across thecorresponding primary winding as the transistor is turned on. When thetransistor is fully on, essentially the entire input DC voltage is seenacross the primary winding. The gate of each transistor is coupled to agate drive winding which is transformer coupled to the primary windingcontrolled by the transistor. The transistor is turned on by chargingits gate capacitance through the gate driving winding. As the transistoris turned on, the voltage across the primary winding increases, therebyincreasing the voltage across the gate drive winding, which turns on thetransistor at an increasingly accelerated rate. After the transistor hasfully turned on, it is switched off by isolating the gate from the gatedrive winding using a capacitor and discharging the gate capacitancethrough a discharge resistor. This turn off process is performed slowlyto reduce EMI radiation.

The production of EMI is further diminished by transformer isolatingboth of the switching transistors from the secondary output windings,thereby allowing the transistors to be configured in a common drainconfiguration.

Power losses during the turn-off process are reduced by operating thetransistor in a soft switching manner thereby reducing powerdissipation.

These and other benefits of the present invention will appear from thefollowing description.

BRIEF DESCRIPTION OF THE DRAWINGS

In the accompanying drawings:

FIG. 1 is a circuit diagram of a preferred push-pull embodiment of theself oscillating power converter of the present invention;

FIG. 2 is a graph showing the voltage across primary transformerwindings T_(B) and T_(C) ;

FIG. 3 is a graph showing the gate voltage of a transistor Q₄ and acrossgate drive transformer winding T_(A) ;

FIG. 4 is a graph showing the gate voltage of a transistor Q₅ and thevoltage across gate drive transformer winding T_(D) ;

FIG. 5 is a graph showing the gate voltage of transistor Q₄, current oftransistor Q₄, and voltage across primary transformer winding T_(B) ;

FIG. 6A is a graph showing the waveform characteristics of the gatevoltage of transistor Q₄ when the power converter is operating in abalanced manner; and

FIG. 6B is a graph showing the waveform characteristics of the gatevoltage of transistor Q₄ during unbalanced operating conditions.

FIG. 7 is a circuit diagram of another embodiment of the selfoscillating power converter of the present invention implemented toreduce the variation of the oscillation frequency when the load or inputvoltage is varied.

FIG. 8 is a circuit diagram of another embodiment of the selfoscillating power converter of the present invention implemented as acommon source push-pull power converter;

FIG. 9 is a circuit diagram of another embodiment of theself-oscillating power converter of the present invention implemented asa push-pull power converter with minimal components;

FIG. 10 is a circuit diagram of another embodiment of the selfoscillating power converter of the present invention implemented as acapacitive coupled push-pull power converter;

FIG. 11 is a circuit diagram of another embodiment of theself-oscillation power converter of the present invention implemented asa hybrid transformer and capacitive coupled push-pull power converter;

FIG. 12 is a circuit diagram of another embodiment of theself-oscillation power converter of the present invention implemented asa transformer coupled full-bridge power converter; and

FIG. 13 is a circuit diagram of another embodiment of theself-oscillation power converter of the present invention implemented asa transformer coupled half-bridge power converter;

FIG. 14 is a circuit diagram of another embodiment of theself-oscillation power converter of the present invention implemented asa hybrid transformer and capacitive coupled full-bridge power converter;and

FIG. 15 is a circuit diagram of another embodiment of theself-oscillation power converter of the present invention implemented asa hybrid transformer and capacitive coupled half-bridge power converter.

DETAILED DESCRIPTION OF PREFERRED EMBODIMENTS

Reference is first made to FIG. 1, which a self oscillating powerconverter circuit 10 made in accordance with a first preferredembodiment of the invention. Power converter 10 is a push-pull converterwhich includes a starter circuit 12, a set of primary transformerwindings T_(B) and T_(C), secondary transformer windings T_(G) and T_(F)and gate drive windings T_(A) and T_(D), MOSFET transistors Q₄ and Q₅,coupling capacitors C₉ and C₁₉, discharging resistors R₁₅ and R₂₃,damping resistors R₂ and R₁, gate stopper resistors R₁₄ and R₂₂, andzener diodes Z₁, Z₂, Z₃, and Z₄.

Starter circuit 12 preferably comprises capacitor C₂₀, resistors R₂₄ andR₂₅, diode D₃, and diac Q₇ as described in U.S. Pat. No. 5,430,632 toMeszlenyi. It should be understood that while this type of startingcircuit is preferred due to its simplicity and low cost, many other wellknown starter circuits may be used to start power converter 10. Due toinevitable slight imbalances in component values (e.g. differences inthe transistor characteristics of Q₄ and Q₅), it would even be possibleto start the circuit simply by raising the DC voltage rapidly across theinput of power converter 10.

Power converter 10 receives DC voltage across terminals IN+ and IN- froma DC source, such as a battery, an AC line power applied through arectifier, an output stage of a power supply, or any time varying sourcehaving constant polarity. Power converter 10 uses primary windings T_(B)and T_(C) and secondary transformer windings T_(G) and T_(F) to isolatethe source from the load. It should be noted that it is possible to havetwo or more sets of secondary windings so that a range of DC outputvoltages can be generated. Further, gate drive windings T_(A) and T_(D)are transformer coupled to primary windings T_(B) and T_(C) and drivethe gates of transistors Q₄ and Q₅.

Drive windings T_(A) and T_(D) should be well-coupled to primarywindings T_(B) and T_(C) (i.e. should have a coupling coefficientgreater than 0.999). Further this coupling should be greater than thecoupling between gate drive winding T_(A) and secondary windings T_(G)or T_(F), and between gate drive winding T_(D) and secondary windingsT_(G) or T_(F) (as secondary windings T_(G) and T_(F) could themselvesbe coupled). This can be achieved by winding the gate drive windingsT_(A) and T_(D) first, winding primary windings T_(B) and T_(C) on topof the gate drive windings and then winding secondary windings T_(F) andT_(G) on top in order to preserve the coupling between primary andsecond windings and associated load regulation. Such coupling ensuresthat the gate drive windings T_(A) and T_(D) will be able to reliablydrive the gates of transistors Q₄ and Q₅ such that oscillation ispreserved and to guard against device failure due to circuitinstability, leakage inductance and ringing currents.

While transistors Q₄ and Q₅ are preferably implemented as n-channelMOSFETs, it should be understood that any type of switching element suchas p-channel MOSFETs, JFETs, BJTs or IGBTs (either p-channel orn-channel) may be used. Because the gates of transistors Q₄ and Q₅ aretransformer isolated, transistors Q₄ and Q₅ can be operated in a commondrain configuration. That is, the drains of transistors Q₄ and Q₅ can betied together to a fixed DC voltage at node IN+ which results in aself-shielding configuration which screens the noise from the rapidlymoving source, as will be explained.

The gates of transistors Q₄ and Q₅ are coupled to gate drive windingsT_(A) and T_(D) by capacitors C₉ and C₁₉ and connected through resistorsR₁₄ and R₂₂, respectively. In turn, capacitors C₉ and C₁₉ are coupled toprimary windings T_(B) and T_(C) through resistors R₁₅ and R₂₃,respectively. This allows the voltage across gate drive windings T_(A)and T_(D) to rise through capacitor C₉ or C₁₉ and to dissipate throughresistor R₁₅ or R₂₃, respectively towards the voltage across primarywindings T_(B) and T_(C) (depending the polarity of the respectivewindings). The values of capacitors C₉, C₁₉ and resistors R₁₅ and R₂₃should be scaled to allow for reasonable power dissipation, as well asreasonable changes in switching speed and frequency due to loadvariation.

Damping resistors R₂ and R₁ are coupled between gate drive windingsT_(A) and T_(D) and capacitors C₉ and C₁₉, respectively. The use ofappropriate values of resistors R₂ and R₁ together with adjustment ofthe transformer turns ratio, can serve to stabilize the operation ofpower converter 10 in an overload situation and to ensure thatsufficient gate drive is provided to transistors Q₄ and Q₅ for full loadoperation.

Gate stopper resistors R₁₄ and R₂₂ are used to damp very high frequencyoscillations (on the order of 100 MHz) and are a conventionally knowncircuit precaution when using MOSFETs. Resistors R₁₄ and R₂₂ create alow pass filter with the gate of the transistors Q₄ and Q₅ which dampsout parasitic instability while at the same time providing sufficientcurrent to drive the gate voltage fast enough.

Zener diode pairs Z₁ /Z₂ and Z₃ /Z₄ are used to clamp the maximumvoltage on the gate of transistors Q₄ and Q₅ to safe limits. While thiseffect could be achieved using a single zener diode, the use of a pairof zener diodes preserves the self-balancing aspect of the oscillator.

When a DC voltage is applied across terminals IN+ and IN-, startercircuit 12 of power converter 10 operates to start power converter 10 asfollows. Capacitor C₂₀ starts to charge with the voltage at terminal IN+through resistor R₂₄. As capacitor C₂₀ is charging, the voltage appliedto diac Q₇ Will increase. Once the applied voltage exceeds its breakdownvoltage, diac Q₇ will begin to conduct current, causing current to flowthrough resistor R₂₅, diode D₃, diac Q₇ and through resistor R₁₄ intothe gate of transistor Q₄. That is, the voltage across capacitor C₂₀will be applied to the gate of transistor Q₄. When the voltage on thegate of transistor Q₄ rises above the turn-on threshold, transistor Q₄will start to turn on. Diode D₃ is a blocking diode which guaranteesthat diac Q₇ will not inadvertently refire.

Once transistor Q₄ begins to conduct, the DC voltage across the IN+ andIN- terminals will be applied directly across primary winding T_(B).Since primary winding T_(B) is transformer coupled to winding T_(A),gate drive winding T_(A) will begin to produce a corresponding voltagehaving a positive polarity (as indicated by the dot). As the voltageacross winding T_(B) increases, the voltage across T_(A) will alsoincrease and will cause increased current to flow through resistor R₂,capacitor C₉ and resistor R₁₄ to the gate of transistor Q₄. Since theincreasingly positive voltage across gate drive winding T_(A) is appliedacross the gate-source junction of transistor Q₄, transistor Q₄ willcontinue to be turned on. This will further increase the voltage acrossprimary winding T_(B) and gate drive winding T_(A). This positivefeedback dynamic serves to turn on transistor Q₄ in an accelerating (orregenerative) manner. As gate drive winding T_(D) has reverse polarityto winding T_(A), when positive DC voltage is applied to winding T_(B),a negative DC voltage will appear across winding T_(D) (at the endopposite to the dot). Since a negative voltage is applied across thegate-source junction of the transistor Q₅, transistor Q₅ will continueto turn off also in a regenerative manner. This process will continueuntil transistor Q₄ is fully on and transistor Q₅ is fully off. Here, ineffect regenerative feedback is applied to both transistors Q₄ and Q₅causing one to turn on and one to turn off.

Once transistor Q₄ is fully on, the full rated DC voltage will appearacross primary winding T_(B) and this DC voltage will remain constant aslong as transistor Q₄ is fully on. At this point, the voltage across thegate capacitance of transistor Q₄ will begin to discharge throughresistor R₁₅. The voltage on the gate of transistor Q₄ will also bedischarged until a turn-off threshold is reached whereby transistor Q₄starts to turn off. Simultaneously, the gate capacitance of transistorQ₅ begins to charge up towards ground through resistor R₂₃. Oncetransistor Q₄ starts to turn off, the turn-over process of powerconverter 10 is initiated and transistor Q₅ will start to turn on, thedetails of which will be described further in relation to the voltageand current characteristics of power converter 10 below.

By alternately turning transistors Q₄ and Q₅ of power converter 10 onand off, the DC voltage across IN+ and IN- is alternately applied acrossprimary windings T_(B) and T_(C). Voltages appear across secondarywindings T_(G) and T_(F) in accordance with the primary/secondarywinding ratio. These voltages are rectified by output stage diodes D₁and D₂ as is conventionally known. The rectified voltage output isapplied across capacitor C₃₆ which provides DC voltage output of powerconverter 10 across terminals OUT+ and OUT-. It is evident that powerconverter 10 cannot be regulated in one stage using conventional meanssuch as PWM or frequency modulation.

FIGS. 2, 3, 4 and 5 together show a number of voltage and currentcharacteristics of transistors Q₄ and Q₅, primary windings T_(B) andT_(C) and gate drive windings T_(A) and T_(D) which result when powerconverter 10 receives a 160 volt DC input at terminals IN+ and IN-, hasa turns ratio of T_(A) to T_(B) (and of T_(D) to T_(C) ) of 1:6 and hascomponents with the following values:

    ______________________________________                                                   Description           Description                                  Designation                                                                              (or Part No.)                                                                            Designation                                                                              (or Part No.)                                ______________________________________                                        C.sub.20   3300 pF    D.sub.1    MUR1620CT                                    R.sub.24   100 kΩ                                                                             D.sub.2    MUR1620CT                                    R.sub.25   475 Ω                                                                              C.sub.36   470 μF                                    D.sub.3    1N 414β                                                       Q.sub.7    diac                                                               R.sub.2    220 Ω                                                                              R.sub.1    220 Ω                                  C.sub.9    2200 pF    C.sub.19   2200 pF                                      Z.sub.1    1N5250     Z.sub.3    1N5250                                       Z.sub.2    1N5250     Z.sub.4    1N5250                                       R.sub.14   22 Ω R.sub.22   22 Ω                                   R.sub.15   475 Ω                                                                              R.sub.23   475 Ω                                  Q.sub.4    IRF740     Q.sub.5    IRF740                                       ______________________________________                                    

FIG. 2 shows the voltages across primary windings T_(B) and T_(C) whichresult when transistors Q₄ and Q₅ are alternately turned on and off. Atpoint A, the voltages across both primary windings T_(B) and T_(C) areat that instant zero. At point A, both gate voltages of transistors Q₄and Q₅ (V_(Q4) and V_(Q5)) are zero and neither transistor is conductivewhich causes zero voltage to be applied to primary windings T_(B) andT_(C). As will be explained, between point A and point C, the gatevoltage V_(Q4) of transistor Q₄ starts to rise (either from beingstarted by starting circuit 12 or during normal oscillation), transistorQ₄ turns on, and the gate voltage of transistor Q₅ starts to fall andtransistor Q₅ turns off. As transistor Q₄ turns on, the DC voltage fromterminals IN+ and IN- starts to be applied across primary winding T_(B)(FIG. 2). As transistor Q₅ turns off, the DC voltage from terminals IN-and IN+ starts to be applied across primary winding T_(C) (FIG. 2). Itshould be noted that once transistors Q₄ and Q₅ are fully on and off,respectively, the voltages across windings T_(B) and T_(C) stay constant(i.e. between points C and D) in spite of non-threshold level variationsin gate voltage.

FIG. 3 shows the voltage across gate drive winding T_(A) and the gatevoltage V_(Q4) of transistor Q₄. The gate voltage V_(Q4) of transistorQ₄ is shown to increase from point A to C (after starting) which in turncauses the voltage across primary winding T_(B) (FIG. 2) to increase ashas been discussed. The voltage across gate drive winding T_(A) (FIG. 3)also increases from point A to point C according to the appropriateturns ratio. The increased voltage across winding T_(A) accelerates theincrease of the gate voltage of transistor Q₄ from point B to C andaccordingly the gate voltage V_(Q4) of transistor Q₄ will follow thevoltage increase across winding T_(A) with a slight delay due to thepresence of the input capacitances of transistors Q₄ and Q₅ andresistors R₂ and R₁₄. The voltage on the gate of transistor Q₄ is drivento a peak voltage value which is limited by zener diodes Z₁ and Z₂.

FIG. 4 shows the voltage across gate drive winding T_(D) and the gatevoltage V_(Q5) of transistor Q₅. The gate voltage of transistor Q₅ isshown to decrease from point A to C which in turn causes the voltageacross primary winding T_(C) (FIG. 2) to decrease as has been discussed.The voltage across gate drive winding T_(D) (FIG. 3) also decreases frompoint A to point C according to the appropriate turns ratio. The voltageacross winding T_(D) drives the gate of transistor Q₅ and accordinglythe gate voltage of transistor Q₅ will follow the voltage decreaseacross winding T_(D) with a slight delay due to the presence ofcapacitor C₁₉ and resistors R₁ and R₂₂. The voltage on the gate oftransistor Q₅ is driven down to a low voltage value which is limited byzener diodes Z₃ and Z₄.

Now referring back to FIGS. 1, 2, 3 and 4, between points A and B, thevoltage across gate drive winding T_(A) and gate voltage V_(Q4) oftransistor Q₄ (FIG. 3) gradually increase. Between points B and C, thevoltages across primary winding T_(B) (FIG. 2) and gate drive windingT_(A) (FIG. 3) increase faster than they did between points A and B.This is due to the fact that the voltage across gate drive winding T_(A)adds to the gate voltage V_(Q4) of transistor Q₄ which in turn increasesthe rate that transistor Q₄ turns on. Between points B and C, the slopeof the voltage of gate voltage V_(Q4) is less than its slope betweenpoints A and B. When transistor Q₄ is driven by a finite sourceimpedance, the miller capacitance must be charged through theresistances of the circuit, as is conventionally known in respect ofMOSFET transistors. This increases the rate at which DC voltage IN+ andIN- is applied to primary winding T_(B) all in an accelerating manner.

An analogous dynamic occurs with respect to primary winding T_(C) (FIG.2) and gate drive winding T_(D) (FIG. 4) in that these voltages bothdecrease in an increasingly rapid manner between points B and C thanbetween points A and B. In this case, between points B and Cincreasingly negative voltage is applied across gate drive winding T_(D)which serves to increase the rate that the transistor Q₅ turns on. Thisincreases the rate at which DC voltage IN- and IN+ is applied to primarywinding T_(C). Between points B and C, the slope of the voltage of gatevoltage V_(Q5) is less than its slope between points A and B. Whentransistor Q₄ is driven by a finite source impedance, the millercapacitance must be discharged through the resistances of the circuit,as is conventionally known in respect of MOSFET transistors.

Referring still to FIGS. 2, 3 and 4, between points C and D, thevoltages across gate drive winding T_(A) and primary winding T_(B) (andcorrespondingly gate drive winding T_(D) and primary winding T_(C) )remain constant as long as transistor Q₄ remains fully on (and as longas transistor Q₅ is fully off). Accordingly, these voltages will beindependent of the gate voltages of transistors Q₄ and Q₅ "voltages oftransistors Q₄ and Q₅ ", add "and capacitor C₉ will have a DC voltageacross it and accordingly will be discharged. Capacitor C₉ will act asan open circuit, effectively isolating the gate of transistor Q₄ fromgate drive winding T_(A) ". After the gate voltage V_(Q4) of transistorQ₄ reaches its peak voltage (FIG. 3), resistor R₁₅ provides a dischargepath for the gate capacitance of transistor Q₄. Accordingly, the gate oftransistor Q₄ will begin to discharge to ground at terminal IN- throughresistor R₁₅ and the gate voltage V_(Q4) of transistor Q₄ (FIG. 3) willexhibit a declining ramp characteristic from points C to D. The voltageat the node between capacitor C₉ and resistor R₁ will display acorresponding declining ramp characteristic and capacitor C₉ will alsobe charged as a result of the voltage across it. This continues untiltransistor Q₄ starts to turn off at point D.

At point D, transistor Q₄ starts to turn off causing a voltage dropacross transistor Q₄ to begin to develop which in turn causes thevoltage across primary winding T_(B) to begin to decrease (FIG. 2).Accordingly, the voltage on gate drive winding T_(A) will follow thevoltage across the primary winding T_(B) and also start to drop (FIG. 3)according to its winding ratio.

At point E, gate voltage V_(Q4) of transistor Q₄ reaches a thresholdvalue and transistor Q₄ begins to come out of its saturation state. Asthe voltage drop across transistor Q₄ substantially increases, thevoltages across primary winding T_(B) and gate drive winding T_(A)continue to decrease. Subsequently, the gate voltage V_(Q4) oftransistor Q₄ begins to rapidly drop due to the effect of rapidlydecreasing gate voltage as a result of decreasing voltage across gatedrive winding T_(A). At this point, the only currents flowing intransistor Q₄ are associated circuit magnetization and leakageinductance currents which serve to drive transistor Q₄ completely offand transistor Q₅ fully on. As the voltage drops across winding T_(B)between points D and E, the voltage across the reverse dottedtransformer coupled gate drive winding T_(D) correspondingly starts torise. Accordingly, at point D, capacitor C₁₉ begins to charge up withthe voltage across gate drive winding T_(D) and applies voltage to thegate of transistor Q₅. The process described above in relation totransistor Q₄ repeats in respect of transistor Q₅, and turn-on oftransistor Q₅ is accelerated between points E to F as transistor Q₅begins to saturate and turn on.

Finally, as previously discussed, just after point F the gate voltageV_(Q4) of transistor Q₄ (FIG. 3) again experiences a smallcharacteristic voltage step commonly associated with MOSFET's. Thiswiggle is due to the charging of the miller capacitance of transistor Q₄through the resistances of the circuit. Specifically, just after point Fon FIG. 3, the miller capacitance of transistor Q₄ is being dischargedand just after point F on FIG. 4, the miller capacitance of transistorQ₅ is being charged.

In this way, a slow turn off process is achieved for transistor Q₄between points D and E (and correspondingly for transistor Q₅ atanalogous points). Traditionally, it has been thought that when atransistor experiences a slow turn-off, significant dissipative powerlosses are inevitable. However, the inventor has discovered that as thegate voltage V_(Q4) of transistor Q₄ decreases between points D and E(FIG. 3) the current flowing through transistor Q₄ essentially stops dueto current conditions present in winding T_(G), as will be explainedbelow.

Now referring to FIG. 5, the current I_(Q4) and the gate voltage V_(Q4)of transistor Q₄ are shown. It should be noted that current I_(Q4) iszero between points D and E. Between points D and E, thetransconductance of transistor Q₄ decreases. That is, as transistor Q₄becomes more resistive, a voltage drop across transistor Q₄ will beproduced. That in turn will mean that the voltage across primary windingT_(B) will be reduced. Since there is an existing voltage across outputterminals OUT+ and OUT-, any drop in voltage across winding T_(B),however slight, will cause the voltage across winding T_(G) to decreasebelow the voltage which exists across capacitor C₃₆ (or across terminalsOUT+ and OUT-). Once this voltage differential is established,rectifiers D₁ and D₂ will stop current flow in the output stage.

Since the current flowing through winding T_(G) is reflected in primarywinding T_(B), the only currents left flowing through primary windingT_(B) will be the magnetization and leakage inductance currents thatwere previously flowing within the transformers and the ringing andparasitic parts of the circuit. Thus, as long as there is an amount ofvoltage across transistor Q₄ between points D and E, current will notflow through transistor Q₄ as is shown between points D and E in FIG. 5.This means that transistor Q₄ essentially operates in a high impedancestate during switch transitions. As the analogous condition exists inrespect of transistor Q₅, both transistors Q₄ and Q₅ of power converter10 assume a high impedance states during switching transitions whichresults in very low overall power dissipation.

Accordingly, power converter 10 provides comparable efficiency to thatof conventional forced oscillating power converters due to its inherentefficiency of operation while achieving softer switchingcharacteristics.

Further, since power converter 10 provides a soft switchingcharacteristic, a significant reduction in the amount of radiated EMI isachieved. In the example implementation of the common-drain selfoscillating power converter 10, the radiated EMI associated with powerconverter 10 was determined to be 40 dB less than the radiated EMIgenerated by a typical forced oscillation power converter. Thisreduction in EMI emissions can be explained by two phenomena.

First, since the voltage across transistor Q₄ drops as the transistor Q₅is turned on and vice versa, minimal ringing is caused in the circuitand leakage spikes are avoided. Further, the slow rise and fall timevoltage waveforms generate less radiated noise and since leakageinductance is not forced to stop suddenly, minimal ringing transientsare produced. As previously discussed, the energy generally produced byleakage inductance is often recovered by adding in extra componentswhich adds to the complexity of the circuit. In the present case, suchmeasures are not required.

Second, since transistors Q₄ and Q₅ are transformer isolated fromsecondary windings T_(F) and T_(G), they can be configured in a commondrain configuration. As is conventionally known, if the voltage on thedrain moves rapidly, the voltage on the large surface area of thetransistor tab changes rapidly causing radiation of EMI noise. Inaddition, since the drain is physically close to the heat sink, it iscapacitively coupled to the heat sink and radiates to the heat sink,causing more radiation of EMI. In a common drain configuration, thevoltage on the drains (the tabs of the transistors) will be stationaryand coupled to the heat sink. Since the sources are physically separatedfrom the heat sink by the drains (having a larger surface area than thesources), a self-shielding effect is produced. It should be noted thatself-oscillating power converters generally have a common-sourceconfiguration in which the drain (on which voltage is moving) provides along path for the high-frequency current and accordingly couples EMInoise to the circuit. In contrast, switching transistors Q₄ and Q₅ ofpower converter 10 are self-shielding and significantly reduce circuitradiated EMI.

A typical balanced power converter contains circuit imbalances which canlead to inefficient or destructive switching conditions. Forcedoscillation power converters attempt to compensate for circuitinequalities by either forcing a switching transistor on longer orshorter than the other switching transistor. If one transistor is lefton longer than another then there is a period where all the circuitcurrents and voltages are forced to stop. If one transistor is left onshorter than another then there is a period of time where bothtransistors will be on which can lead to destruction of the circuit. Incontrast, the self oscillating dynamic allows each transistor to switchat its own speed which results in optimal right turn-on and turn-offcurrent and voltage characteristics and a soft switch dynamic. While itis conventionally known that slow switching generally causes a highamount of power dissipation, the soft switching achieved by powerconverter 10 generates low power dissipation due to zero transistorcurrents during switching transitions.

Power converter 10 also exhibits self-balancing behaviour which preventsdestructive core saturation. Typical push-pull converters must maintaina zero DC component across each half-winding (otherwise flux densitybuilds in the transformer). When the on-time and off-time of switchingtransistors are not exactly equal, increased volt seconds will tend tobuild up across one of the two winding with each cycle. This will resultin an increase in core flux until the core finally saturates.

FIG. 6A illustrates the gate voltage of transistor Q₄ of power converter10 under balanced conditions where the on-time and off-time oftransistors Q₄ and Q₅ are equal. Accordingly, the average voltage willbe zero. Since gate drive windings T_(A) and T_(D) are transformercoupled, no net DC voltage can be generated and thus the average voltageon each gate drive winding must be zero. If the on-time and off-time oftransistors Q₄ and Q₅ are unequal (FIG. 6B) then non-equal volt secondswill tend to shift the DC operating point of the gate drive voltagewaveforms in the negative direction such that the volts seconds acrossthe gate drive windings T_(A) and T_(D) will re-equalize. In the caseshown in FIG. 6B, the resulting gate voltage V_(Q4) will result intransistor Q₄ turning off sooner to rebalance power converter 10.

As an illustration, if resistor R₁₅ has a larger value than R₂₃, then itwill take longer to discharge capacitor C₉ than it will to dischargecapacitor C₁₉. Thus, the on-time for Q₄ will be longer than the on-timefor Q₅. Thus, the voltage at the gate of transistor Q₄ (or the voltageacross gate drive winding T_(A) ) can be represented by the waveform ofFIG. 6B. Due to the fact that the circuit is AC coupled (throughcapacitors C₉ and C₁₉), the areas under the voltage waveform must beequal. Therefore, resistor R₁₅ will have to discharge C₉ and the gatecapacitance of transistor Q₄ less to reach the transistor turn-offthreshold as the threshold voltage for transistor Q₄ will be lowered(see FIG. 6B). Thus, even if transistor Q₄ starts off being on longerthan transistor Q₅, the circuit will rapidly rebalance itself. Thisfeature is important, since in practice, there are many small circuitparameters which can cause a circuit imbalance (such as the values ofthe capacitors and resistors, the leakage inductance of windings T_(A)and T_(D), etc.)

Finally, a built-in safety feature prevents damage of power converter 10due to core saturation (due to improper design parameters,inappropriately slow switching frequencies, etc.) In the case where thecore begins to saturate, the voltage on the appropriate gate drivewinding T_(A) or T_(D) will rapidly drop. This will initiate turnoff oftransistor Q₄ or Q₅ and turnon of the complimentary transistor, whichwill alleviate the core saturation.

Referring now to FIG. 7, a second exemplary self oscillating powerconverter circuit 50, made in accordance with the present invention.This circuit contains identical components to those of power converter10 of FIG. 1 and they are identified as such. While starting circuit 12is not shown, it should be understood that starting circuit 12, or anyequivalent circuit, could be implemented within power converter 50 asbefore. The only difference between power converter 50 and powerconverter 10 is that coupling capacitor C₉ has been moved and is nowcoupled between zener diode Z₁ and resistor R₁₄. Coupling capacitor C₁₉is similarly coupled between zener diode Z₄ and resistor R₂₂.

In power converter 10, the oscillating frequency will vary, depending onthe load coupled at terminals OUT+ and OUT-. A higher load will resultin a lower voltage across gate drive winding T_(A) (and across gatedrive winding T_(D)). This will in turn result in a lower voltage acrosscoupling capacitor C₉, which will have a commensurately lower charge onit. Coupling capacitor will discharge more quickly through resistor R₁₅,as described above (between points C and D in FIGS. 2-5). Transistor Q₄will begin to turn off earlier (i.e. point D will occur sooner), and theoscillating frequency of power converter 10 will be higher. Couplingcapacitor C₁₉, resistor R₂₃ and transistor Q₅ will exhibit the samebehaviour during the other half of the oscillation cycle of powerconverter 10.

In power converter 10, the oscillating frequency also has an inverserelationship to the magnitude of the input DC voltage across terminalsIN+ and IN-. A greater input DC voltage will result in a greater voltageacross primary winding T_(B) when transistor Q₄ is conducting and acrossprimary winding T_(C) when transistor Q₅ is conducting. This will inturn result in a greater voltage across gate drive windings T_(A) andT_(D), with the opposite effect to that described above in the case ofan increased load.

In power converter 50, the dependency of oscillating frequency on boththe load and the input DC voltage is diminished by using zener diodes Z₁and Z₂ to clamp the voltage across gate drive winding T_(A). Thisessentially fixes the maximum voltage across coupling capacitor C₉,substantially reducing the effects of varying either the load or theinput DC voltage.

To enjoy the benefit of this improvement, zener diodes Z₁ and Z₂ and theturns ratio of T_(A) to T_(B) must be selected to ensure that zenerdiode Z₁ is reverse biased (i.e. it is operating in its breakdownregion). The capacitance of capacitor C₉ must also be increased tocompensate for the reduced drive voltage across it. This improvementalso allows the resistance of damping resistor R₂ to be increased,resulting in lower power dissipation in power converter 50 andincreasing the stabilizing effect of the resistor. It will be apparentthat similar components selections must be selected for zener diodes Z₃and Z₄, coupling capacitor C₁₉ and damping resistor R₁ to retain thebalanced operation of power converter 50.

The inventor has found that selecting components with the followingvalues provides a suitable operation for power converter 50:

    ______________________________________                                        Designation          Description                                              ______________________________________                                        Z.sub.1              12 volt                                                  Z.sub.2              12 volt                                                  Z.sub.3              12 volt                                                  Z.sub.4              12 volt                                                  R1                   475 Ω                                              R.sub.2              475 Ω                                              C.sub.9              4700 pF                                                  C.sub.19             4700 pF                                                  ______________________________________                                    

The remaining components of power converter 50 may be identical to thosepreviously listed for power converter 10. The inventor has found thatthe same turns ratio of T_(A) to T_(B) of 1:6 provides suitable resultswhen the input DC voltage is 160 volts (as before). Analogous voltageand current characteristics will be generated by power converter 50 aswere discussed in respect of power converter 10. Accordingly, thebenefits of efficiency and self-balancing apply equally to powerconverter 50, as previously discussed. In addition, power converter 50has the same common-drain configuration as power converter 10 and willshare the benefits of EMI reduction of power converter 10.

Referring now to FIG. 8, a common source push-pull power converter 100is shown. This circuit contains identical components to those of powerconverter 50 of FIG. 7 and they are identified as such. The maindifference between power converter 100 and power converter 50 of FIG. 7,is that transistors Q₄ and Q₅ of power converter 100 have acommon-source configuration, as is conventionally understood. That is,the sources of transistors Q₄ and Q₅ are tied together to terminal IN-.

Once power converter 100 is started and transistor Q₄ starts to turn on,the voltage across IN- and IN+ will be applied across primary windingT_(B). This in turn will generate a positive voltage across gate drivewinding T_(A) (on the end opposite to the dot) which will, in turn serveto further drive on the gate of transistor Q₄. This increasing positivevoltage is applied across the gate-source junction of transistor Q₄which increases the rate at which transistor Q₄ turns on.Simultaneously, a negative voltage will be generated across gate drivewinding T_(D) (with respect to the dot) which will further drivetransistor Q₅ off. Analogous voltage and current characteristics will begenerated by power converter 100 as were discussed in respect of powerconverter 10. Accordingly, the benefits of efficiency and self-balancingapply equally to power converter 100, as previously discussed.

However, since power converter 100 does not have the self-shieldingbenefits of a common-drain configuration, the benefits of EMI reductionof power converter 10 are not shared by power converter 100. Aspreviously mentioned, the drains are the tabs of the transistors (whichhave a physically large surface area). Since there is fast movingvoltage on the drains and since the drains are capacitively coupleddirectly to the heat sink, a high frequency current is generated whichcirculates within the circuit. This high frequency current travelsthrough a lengthy circuit path and represents a significant EMIradiation source. However, it should be noted that EMI reductions couldstill be realized within power converter 100 by using p-channeltransistor devices.

Referring now to FIG. 9, a push-pull power converter 200 is shown whichuses minimal components and which has a common-drain configuration. Allcomponents shown are identical to those of power converter 10 of FIG. 1.However, gate stopper resistors R₁₄ and R₂₂ of FIG. 1 are not used asthey are not necessary when the circuit is designed to avoid highfrequency oscillations (greater than 100 MHz). Further, dampingresistors R₂ and R₁ of FIG. 1 are not included, since it is possible toconfigure the transformer windings so that resistors R₂ and R₁ are notneeded to control the effect of leakage inductances. Finally, zenerdiodes Z₁, Z₂, Z₃, and Z₄ are not included as they are not needed if thecircuit is designed to prevent the voltage from going higher than theallowable voltage limits for the gate of transistors Q₄ and Q₅. Itshould be noted that while power converter 200 is shown to have acommon-drain configuration, as indicated above, it would also bepossible to implement converter 200 in a common-source configuration.

Once power converter 200 is started (with a conventional startercircuit) and transistor Q₄ starts to turn on, the voltage acrossterminals IN- and IN+ will be applied to primary winding T_(B). This inturn will generate a positive voltage across gate drive winding T_(A)(with respect to the dot) which will, in turn serve to further drive thegate of transistor Q₄ which will increase the rate at which transistorQ₄ turns on. Simultaneously, a negative voltage will be generated acrossgate drive winding T_(D) (on the end opposite to the dot) which willfurther drive transistor Q₅ off. Analogous voltage and currentcharacteristics will be generated by power converter 200 as werediscussed in respect of power converter 10, as would be conventionallyunderstood in the absence of resistors R₁, R₂, R₁₄, R₂₂ and zener diodesZ₁, Z₂, Z₃, and Z₄. Accordingly, all the benefits of efficiency, reducedEMI emissions and self-balancing apply equally to power converter 200,as previously discussed in respect of power converter 10.

Referring now to FIG. 10, a push-pull power converter 300 is shownhaving a common-source configuration. This circuit contains identicalcomponents to those of power converter 50 of FIG. 7 and they areidentified as such. Power converter 300 capacitively couples the gatesof transistor Q₄ and Q₅ to the opposing legs of the push-pull circuit.It should be noted that the process of charging and dischargingcapacitors C₉ and C₁₉ through resistors R₁₅ and R₂₃, respectively isstill incorporated into the design of power converter 300. While thisembodiment does not have the EMI reduction or self-balancing features orthe core saturation protection of power converter 10, the parasiticeffects associated with gate drive transformers have been eliminated andthere are fewer parts.

Once power converter 300 is started and transistor Q₄ starts to turn on,the voltage across terminals IN- and IN+ will be applied across primarywinding T_(B). Transistor Q₄ will then conduct and connect terminal IN-with the gate of transistor Q₅ through capacitor C₁₉ and transistor Q₅will be hard driven off. Once the voltage across capacitor C₉ startsdischarging through resistor R₁₅ to terminal IN- past the threshold oftransistor Q₄, transistor Q₄ will start turning off. As transistor Q₄starts to turn off, this will cause the voltage on the drain of Q₄ toclimb relative to the terminal IN-. This will cause current to flowthrough capacitor C₁₉ which will in turn flow into the gate oftransistor Q₅ to turn on transistor Q₅.

Accordingly, as transistor Q₅ starts to turn on, the voltage on thedrain of transistor Q₅ will begin drop. By virtue of the magnetizationcurrents within the circuit, this will cause the voltage at capacitor C₉to decrease due to increased current flow out of the gate of transistorQ₄ which serves to accelerate the turn-off of transistor Q₄. At the sametime, the voltages across capacitor C₁₉ and at the gate of transistor Q₅will start to discharge through resistor R₂₃ until the threshold voltageis met and transistor Q₅ starts to turn off. As transistor Q₅ starts toturn off, this will cause the voltage on the drain of transistor Q₅ torise relative to the terminal IN-. This will cause current to flowthrough capacitor C₉ into the gate of transistor Q₄ to turn ontransistor Q₄ wherein the process will repeat itself.

It should be noted that power converter 300 does not allow forsoft-switching as was the case with transformer coupled power converters10, 50, 100 and 200, since in converter 300 the rate of switching is nolonger controlled by the rate at which voltage is applied across gatedrive windings T_(A) and T_(D) (i.e. the transformer characteristic). Itshould also be noted that this embodiment cannot be implemented usingcommon drain configuration using n-channel transistors Q₄ and Q₅ butthat a common-drain embodiment could be built using p-channeltransistors. Power converter 300 achieves efficiency by switching fastand hard and achieves a reduced parts count as it can be easily builtout of few parts and the transformer can be easily constructed.

Referring now to FIG. 11, a push-pull power converter 400 is shownhaving a combination of a capacitively coupled gate drive and atransformer gate drive, as have been discussed previously. This circuitcontains identical components to those of power converter 50 of FIG. 7and they are identified as such. Transistors Q₄ and Q₅ of powerconverter 400 have a common-source configuration. While power converter400 is more prone to becoming unbalanced due to the mixed nature of thecircuit (e.g. the circuit coupled side may switch faster than thetransformer coupled side), circuit component values can be adjusted tocompensate for any switching mismatch between the gate drives. Further,the restoring effects of the transformer coupled section providesignificant circuit stability.

Once power converter 400 is started and transistor Q₄ starts to turn on,the voltage across terminals IN- and IN+ will be applied to primarywinding T_(B). A negative voltage will then be generated acrosstransformer coupled gate drive transformer T_(A) (with respect to thedot) which will increasingly drive transistor Q₅ off. Once the voltageacross capacitor C₉ starts discharging through resistor R₁₅ to terminalIN- past the threshold of transistor Q₄, transistor Q₄ will startturning off. As transistor Q₄ starts to turn off, this will cause thevoltage on the drain of Q₄ to climb relative to the terminal IN-. Thiswill cause the voltage across primary winding T_(B) to decrease andaccordingly the voltage across gate drive winding T_(A) will alsodecrease. This will cause a positive voltage to build up on capacitorC₁₉ which will in turn drive the gate of transistor Q₅ to turn ontransistor Q₅.

Accordingly, as transistor Q₅ starts to turn on, the voltage on thedrain of transistor Q₅ will begin drop. By virtue of the magnetizationcurrents within the circuit, the voltage at capacitor C₉ will decreasedue to increased current flow out of the gate of transistor Q₄ whichserves to accelerate the turn-off of transistor Q₄. At the same time,gate drive winding T_(A) will accelerate the turn on of transistor Q₅.Once transistor Q₄ is fully off and transistor Q₅ is fully on, thevoltages across capacitor C₁₉ and at the gate of transistor Q₅ willstart to discharge through resistor R₂₃ until the threshold voltage ispassed and transistor Q₅ starts to turn off. As transistor Q₅ starts toturn off, this will cause the voltage on the drain of transistor Q₅ torise relative to the terminal IN-. This will cause current to flowthrough capacitor C₉ into the gate of transistor Q₄ to turn ontransistor Q₄ wherein the process will repeat itself.

FIG. 12 shows a full bridge power converter 500 with four transformercoupled drive circuits for transistors Q_(1'), Q_(2'), Q_(4') andQ_(5'). Each transformer drive circuit contains a gate drive transformerwinding (T_(A'), T_(D'), T_(A"), or T_(D")), a capacitor (C_(9'),C_(19'), C_(1'), or C_(2')), zener diode pairs (Z_(1'), and Z_(2'),Z_(3') and Z_(4'), Z_(5') and Z_(6'), or Z_(7') and Z_(8')), and aresistor (R_(15'), R_(23'), R_(1'), or R_(2')), respectively. As shown,power converter 500 has one primary winding T_(B') which can be orientedin both polarities such that orientation is reversed for each cycle. Asis conventionally known, diagonal pairs of transistors (i.e. transistorsQ_(4'), and Q_(2') and transistors Q_(1') and Q_(5')) will alternatelyconduct, thus achieving current reversal in the transformer primarywinding T_(B').

Once transistors Q_(2') and Q_(4') start to turn on (using a startingcircuit or the like), the voltage across terminals IN- and IN+ will beapplied across primary winding T_(B'). This in turn will generatepositive voltages across gate drive windings T_(A') and T_(D") (withrespect to the dot) which will, in turn serve to further drive the gatesof transistors Q_(4') and Q_(2') respectively. This will increase therate at which transistors Q_(4') and Q_(2') turn on. Simultaneously,negative voltages will be generated across gate drive windings T_(D')and T_(A") (on the end opposite to the dot) which will further drivetransistors Q_(5') and Q_(1') off, respectively. At this point currentflow will be `downwards` through primary winding T_(B').

Once the voltages across capacitors C_(9') and C_(2') start dischargingthrough resistors R_(15') and R_(2') to terminals IN+ and IN-,respectively, and reach the threshold of transistors Q_(4') and Q_(2'),transistors Q_(4') and Q_(2') will start turning off and the voltageacross primary winding T_(B') will start to drop. Simultaneously, apositive voltage will be generated across gate drive windings T_(D') andT_(A") (on the end opposite to the dot) which will drive the gates oftransistors Q_(5') and Q₁, to turn on respectively. The voltage betweenterminals IN+ and IN- will be applied across primary winding T_(B') inan opposite manner as before and an increased positive voltage (on theend opposite the dot) will appear across gate drive windings T_(D') andT_(A"). Accordingly, an acceleration in the rate at which transistorsQ_(5') and Q_(1') turn on will result. Simultaneously, negative voltageswill be generated across gate drive windings T_(A') and T_(D") (at thedot) which will further drive transistors Q₄ and Q_(2') off,respectively. At this point current flow will be `downwards` throughprimary winding T_(B').

Since power converter 500 embodies four transformer coupled transistors,all the benefits of efficiency, reduced EMI emissions and self-balancingdiscussed in association with power converter 10 apply equally to powerconverter 500.

FIG. 13 shows half-bridge power converter 600 with two transformercoupled drive circuits for transistors Q_(4') and Q_(5'). Half-bridgepower converter 600 is identical to full-bridge power converter 500except for the replacement of transistor Q_(1'), capacitor C_(1'), gatedrive winding T_(A"), zener diodes Z_(5') and Z_(6') and resistorR_(1'), with capacitor C₃₈ and transistor Q_(2'), capacitor C_(2'), gatedrive winding T_(D"), zener diodes Z_(7') and Z_(8') and resistor R_(2')with capacitor C₄₀ as shown, to form an AC-coupled return path. Powerconverter 600 has one primary winding T_(B') which can be oriented inboth polarities such that orientation is reversed for each cycle, as isconventionally known. Transistors Q_(4') and Q_(5') will alternatelyconduct, thus achieving current reversal in the transformer primarywinding T_(B').

Since power converter 600 embodies two transformer coupled transistors,all the benefits of efficiency, reduced EMI emissions and self-balancingdiscussed in association with power converter 10 apply equally to powerconverter 600.

FIG. 14 shows a full-bridge power converter 700 having two capacitivelycoupled drive circuits for transistors Q_(5') and Q_(2') and twotransformer coupled drive circuits for transistors Q_(4') and Q₁. Thiscircuit contains identical components to those of power converter 500 ofFIG. 11 and they are identified as such with the exception that gatedrive windings T_(D') and T_(D") are not included.

As shown, power converter 700 has one primary winding T_(B') which canbe oriented in both polarities such that orientation is reversed foreach cycle. As is conventionally known, diagonal pairs of transistors(i.e. transistors Q_(4') and Q_(2') and transistors Q_(1') and Q_(5'))will alternately conduct, thus achieving current reversal in thetransformer primary winding T_(B').

Once the voltage across capacitor C_(9') starts discharging throughresistor R_(15') to terminal IN- past the threshold of transistor Q'₄,transistor Q_(4') will start turning off. As transistor Q_(4') starts toturn off, this will cause the voltage on the drain of Q_(4') to climbrelative to the terminal IN-. This will cause the voltage across gatedrive winding T_(B') cause a voltage to build up on capacitor C_(19')which will in turn drive the gate of transistor Q_(5') to turn ontransistor Q_(5').

Once transistors Q_(2') and Q_(4') start to turn on (using a startingcircuit or the like), the voltage across terminals IN- and IN+ willbegin to be applied across primary winding T_(B'). This in turn willgenerate a positive voltage is generated across gate drive windingT_(A') (with respect to the dot) which will, in turn serve to furtherdrive the gates of transistors Q_(4') which will increase the rate atwhich transistors Q_(4') turns on. Similarly, a negative voltage isgenerated across gate drive winding T_(A") (on the opposite end of thedot) which ensures the turn-off of transistor Q_(1'). Simultaneously,terminal IN+ is connected to the gate of transistor Q_(2') throughcapacitor C_(2') and is driven hard on. As transistor Q_(2') starts toturn on, terminal IN- is coupled to the gate of transistor Q_(5')through capacitor C_(19') and transistor Q_(5') will be hard driven off.At this point current flow will be `downwards` through primary windingT_(B').

Once the voltages across capacitors C_(9') and C_(2') start dischargingthrough resistors R_(15') and R_(2') to terminal IN- past the thresholdof transistors Q_(4') and Q_(2') transistors Q_(4') and Q_(2') willstart turning off. As transistor Q₄ starts to turn off the voltageacross primary winding T_(B') is reduced and the positive voltage acrossgate drive winding T_(B') and the negative voltage across gate drivewinding T_(A") are both reduced to assist in the turn-off transitions oftransistor Q₄ and the turnon transition of transistor Q_(1').Simultaneously, as transistor Q_(2') starts to turn off, this will causethe voltage on the drain of Q_(5') to climb relative to the terminalIN-. This will cause current to flow through capacitor C_(19') whichwill in turn flow into the gate of transistor Q_(5') to turn ontransistor Q_(5'), wherein the process will repeat itself. At this pointcurrent flow will be `upwards` through primary winding T_(B').

Since power converter 700 includes two coupled capacitor transistors,the benefits of reduced EMI emissions and self-balancing discussed inassociation with power converter 10 do not apply to power converter 700.However, power converter 700 still provides an efficient and low costimplementation.

FIG. 15 shows half-bridge power converter 800 with two transformercoupled drive circuits for transistors Q_(4') and Q_(5'). Half-bridgepower converter 800 is identical to full-bridge power converter 700except for the replacement of transistor Q_(1'), capacitor C_(1'), gatedrive winding T_(A"), zener diodes Z_(5') and Z_(6') and resistorR_(1'), with capacitor C₃₈ and transistor Q_(2'), capacitor C_(2'),zener diodes Z_(7') and Z_(8') and resistor R_(2') with capacitor C₄₀ asshown, to form an AC-coupled return path. Power converter 800 has oneprimary winding T_(B') which can be oriented in both polarities suchthat orientation is reversed for each cycle, as is conventionally known.Transistors Q_(4') and Q_(5') will alternately conduct, thus achievingcurrent reversal in the transformer primary winding T_(B').

Since power converter 800 embodies two capacitor coupled transistors,the benefits of reduced EMI emissions and self-balancing discussed inassociation with power converter 10 do not apply to power converter 800.However, power converter 800 still provides an efficient and low costimplementation.

In summary, various embodiments of the present invention provide anumber of advantages. First, power converter 10 can achieve comparablepower efficiencies to forced oscillator power converters while usingfewer electronic components then are typically associated with forcedoscillating approaches. The self-optimized switching speeds which resultfrom the regenerative nature of the gate drive mechanism allows powerconverter 10 to achieve slower switching speeds without any loss ofefficiency. Accordingly, power converter 10 generates significantlyreduced EMI emissions without sacrificing power efficiency. Further, EMIis reduced in the common-drain configuration of power converter 10 asthe drains of the transistors prevent capacitive coupled noise frombeing generated by the rapidly moving source. Finally, power converter10 has a self-balancing feature which serves to alter the gate drivewaveforms to achieve a balanced transistor switching characteristic.

As is conventionally understood, power converter 10 can be provided withadditional transformer windings for multiple device outputs or it can befront-end integrated with various filters or conditioning apparatus.Further, it should be noted that the frequency range of operation ofpower converter 10 can be affected by changing the turns ratio ofvarious winding pairs, improve the coupling, change resistance, changecapacitances, can change values of resistors, capacitors etc. Theinventor has found it preferable to run power converter 10 at between 90and 250 KHz. Further, the DC voltage provided by power converter 10 canbe varied to comply with application requirements by adjusting thetransformer turns ratio, as is conventionally known. The inventor hasfound that power converter 10 can be operated to produce voltage between5 to 500 volts.

As will be apparent to persons skilled in the art, various modificationsand adaptations of the structure described above are possible withoutdeparture from the present invention, the scope of which is defined inthe appended claims.

I claim:
 1. A self oscillating power converter circuit having:(a) asource of direct current voltage; (b) a drive transformer having firstand second primary windings and a first control terminal winding forgenerating a first control voltage, said first control terminal windingbeing transformer coupled to said first primary winding; (c) first andsecond transistors connected across said first and second primarywindings, said first transistor having a first control terminal coupledto said first control terminal winding, said first control terminalhaving a first control terminal capacitance, said first control terminalcapacitance being charged in response to said first control voltage, andsaid first and second transistors alternately being turned on and off;(d) a first feedback path for said first transistor including said firstcontrol terminal winding, said first control terminal winding beingphased with said first primary winding such that said direct currentvoltage provides regenerative feedback at said first transistor controlterminal; (e) a first resistance coupled between said first controlterminal and said first primary winding for discharging said firstcontrol terminal capacitance, and; (f) a first coupling capacitancecoupled to said first transistor control terminal for allowing saidfirst control terminal capacitance to be discharged through said firstresistance,wherein said first resistance is coupled in parallel with thecombination of said first control terminal winding and said firstcoupling capacitance and wherein said first transistor turns on inresponse to the charging of said first control terminal capacitance andturns off in response to the discharging of said first control terminalcapacitance.
 2. The circuit of claim 1, wherein said second transistorhas a second control terminal and a second feedback path which includesa second control terminal winding for generating a second controlvoltage, said second control terminal having a second control terminalcapacitance, said second control terminal capacitance charging inresponse to said second control voltage, said second control terminalwinding being phased with said second primary winding such that saiddirect current voltage provides regenerative feedback at said secondcontrol terminal, a second resistance being coupled between said secondcontrol terminal and said second primary winding for discharging saidsecond control terminal capacitance, said feedback path including asecond coupling capacitance coupled to said second control terminal forallowing said second control terminal capacitance to be dischargedthrough said second resistance wherein said second resistance is coupledin parallel with the combination of said second control terminal windingand said second coupling capacitance and wherein said second transistorturns on in response to said charging of said second control terminalcapacitance and turns off in response to said discharging of saidcontrol terminal capacitance.
 3. The circuit of claim 2, further havinga voltage limiting circuit coupled between said first control terminaland said first primary winding and between said second control terminaland said second primary winding for limiting the voltage applied at saidfirst and second control terminals.
 4. The circuit of claim 2, furtherhaving a voltage limiting circuit coupled between said first controlterminal and said first primary winding and between said second controlterminal and said second primary winding for limiting the voltage acrosssaid first and second control terminal windings.
 5. The circuit of claim3 or 4, wherein said voltage limiting circuit includes a backward biasedzener diode pair.
 6. The circuit of claim 2 further having a dampingcircuit coupled between said first control terminal winding and saidfirst coupling capacitance and between said second control terminalwinding and said second coupling capacitance for reducing high frequencyoscillations within converter.
 7. The circuit of claim 6 wherein saiddamping circuit includes a resistor.
 8. The circuit of claim 2 furtherhaving a gate stopper circuit coupled between said first controlterminal and said first coupling capacitor and between said secondcontrol terminal and said second coupling capacitor for reducing highfrequency oscillations within said converter.
 9. The circuit of claim 8wherein said gate stopper circuit includes a resistor.
 10. The circuitof claim 1 or 2 wherein said transistors are MOSFET transistors.
 11. Thecircuit of claim 10 wherein said MOSFET transistors are connected in acommon drain configuration.
 12. The circuit of claim 1 wherein saidfirst primary winding and said first control terminal winding have acoupling coefficient greater than 0.999.
 13. The circuit of claim 2wherein said second primary winding and said second control terminalwinding have a coupling coefficient greater than 0.999.
 14. The circuitof claim 2 further having a pair of secondary windings for coupling saidcircuit to a load such that the coupling coefficient of said first andsecond control terminal windings to said first and second primarywindings is higher than the coupling coefficient of said first andsecond control terminal windings to said secondary windings.
 15. Thecircuit of claim 1 further having a starter circuit for initiatingoscillations in said converter by applying a start-up signal to one ofsaid first and second transistors.
 16. A self oscillating powerconverter circuit having:(a) a source of direct current voltage; (b) adrive transformer having first and second primary windings; (c) firstand second transistors connected across said first and second primarywindings, said first transistor having a first control terminal, saidsecond transistor having a second control terminal, said first controlterminal having a first control terminal capacitance and said secondcontrol terminal having a second control terminal capacitance: (d) afirst feedback path for said first transistor including a first couplingcapacitor and said first and second primary windings and a secondfeedback path for said second transistor including a second couplingcapacitor and said first and second primary windings; and (e) a firstresistor coupled to said first control terminal and to said secondtransistor for discharging said first control terminal capacitance and asecond resistor coupled to said second control terminal and to saidfirst transistor for discharging said second control terminalcapacitance,wherein said first resistor is coupled in parallel with saidfirst coupling capacitor and said second resistor is coupled in parallelwith said second coupling capacitor.
 17. A self oscillating powerconverter circuit having:(a) a source of direct current voltage; (b) adrive transformer having a primary winding and a first control terminalwinding for generating a first control voltage, said first controlterminal winding being transformer coupled to said primary winding; (c)first and second transistors connected across said primary winding, saidfirst and second transistors alternately turning on and off, said firsttransistor having a first control terminal coupled to said first controlterminal winding and said first control terminal having a first controlterminal capacitance, said first control terminal capacitance beingcharged in response to said first control voltage; (d) a first feedbackpath for said first transistor including said first control terminalwinding, said first control terminal winding being phased with saidprimary winding such that said direct current voltage providesregenerative feedback at said first transistor control terminal; (e) afirst coupling capacitance coupled to said first transistor controlterminal within said first feedback path for allowing said first controlterminal capacitance to be discharged; and (f) a first resistor coupledto said first control terminal and to said primary winding fordischarging said first control terminal capacitance,wherein said firstresistor is coupled in parallel with the combination of said firstcontrol terminal winding and said first coupling capacitance and whereinsaid first transistor turns on in response to the charging of said firstcontrol terminal capacitance and turns off in response to thedischarging of said first control terminal capacitance.
 18. The circuitof claim 2 wherein said circuit further comprises:(a) a first outputwinding and a second output winding, said first output winding beingtransformer coupled to said first primary winding and said second outputwinding being transformer coupled to said second primary winding; afirst output terminal and a second output terminal, each of said outputterminals being coupled to each of said first output winding and saidsecond output winding,wherein an output direct current voltagecorresponding to said source of direct current voltage is available atsaid first and second output terminals.
 19. The circuit of claim 18wherein:(a) a first rectifier is coupled between said first outputwinding and said first output terminal for rectifying a first outputhalf-wave appearing across said first output winding; and (b) a secondrectifier is coupled between said second output winding and said firstoutput terminal for rectifying a second output half-wave appearingacross said second output winding,wherein said output direct currentvoltage is a full wave voltage.
 20. The circuit of claim 19 wherein anoutput capacitor is coupled between said first output terminal and saidsecond output terminal.